A semiconductor device may have a construction such as a bipolar IC or Metal Oxide Silicon (MOS) IC. Such a semiconductor device may be used as a switch or memory in various devices.
FIG. 1 is an example diagram illustrating a related art semiconductor device.
Referring to FIG. 1, substrate 1 may be a p-type silicon substrate. To define an active region of substrate 1, field layers 2 and 3 may be formed at a field area of substrate 1.
Gate oxide layer 6 may be grown on substrate 1, for example by a thermal oxidization. Polysilicon 7 may be deposited on gate oxide layer 6, for example by chemical vapor deposition (CVD). Next, polysilicon 7 and gate oxide layer 6 may be patterned by a photolithograph process to form gate 7.
An insulating layer may be thickly formed and etched on substrate 1 on which gate 7 may be formed, and may form sidewall 8 at a sidewall of the gate. N-type impurity ions (e.g. arsenic As) may be implanted in the resulting object, for example using sidewall 8 as a mask to form source/drain 4 and 5.
In a semiconductor device, a variation of a critical dimension CD in a gate may significantly change a drive current of a semiconductor device. Accordingly, an optimization of the CD in the gate may be important.
For example, as a CD of a gate is increased, a driver current may be reduced. Thus a CD of a gate may be inversely proportional to a drive current. Because an amplitude of the drive current may control an operation speed of the semiconductor device, a variation of a CD in the gate may affect an overall operation of the semiconductor device. Precise management of a CD in a gate may determine a quality of a semiconductor device.
Furthermore, a variation of a CD in a gate may cause an increase in a leakage current and a reduction in saturation current.
Referring to FIG. 2, gate oxide layer 6 and polysilicon 7 may have been formed on substrate 1. The resulting object may then be coated with a photoresist material. Next, the photoresist material may be exposed to light using mask pattern 13 to form photoresist pattern 11. A resulting object may be etched using photoresist pattern 11 as a mask to form gate 7.
Where gate 7 by the aforementioned process may be formed, photoresist pattern 11 may be formed to exactly have a size of ‘a’ by mask pattern 13. Nevertheless, when an etching process is performed using photoresist pattern 11 having an exact size of ‘a’ as a mask, a size of a gate may be changed to a±2 b which is not ‘a’ due to an etching bias.
Hence, in the related art, as a size of the gate may be increased or reduced in comparison with a desired size, a CD of the gate may be changed. As a result, as the drive current varies, an operation speed of the semiconductor device they become non-uniform, and may result in instability of a device characteristic.